Slavica Malobabić

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Contact Information:

• Email: smalobabic@ieee.org

Education

• PhD studies in Electrical Engineering – Presidential Fellowship University of Central Florida (UCF), GPA 4 / 4, Advisor: Dr. Juin J. Liou. Expected graduation date Fall 2011.
• Master's studies, Major Solid State Electronics GPA 5 / 5, top 5% of graduating class Simon Bolivar University (USB), Caracas, Venezuela, October 2006. Advisor: Dr. Adelmo Ortiz-Conde.
• Professional Electronics Engineer Degree (5 year program) GPA 4.69 / 5, top 5% of graduating class, USB, January 2005. Advisor: Dr. Adelmo Ortiz – Conde.

Experience

• June 2007 – Ongoing · Research assistant, University of Central Florida (UCF) and Analog Devices (ADI) as part of long term project: “Failure criteria metric under ESD stress conditions” with University of Central Florida. Topics: Device simulation in DC and ESD regime, Gate oxide breakdown characterization and Development of design guidelines and failure metrics under Human Metal Model (HMM) and IEC type stresses for ESD structures and DMOS devices. Software used by Synopsys, Sentaurus tools. Instruments: TLP, VFTLP tester, Keithley 4200, Hanwa HMM tester, Teseq ESD gun.
• October 2009 · Created and recorded a 1.5 hour educational video to instruct new students on the typical ESD characterization equipment (TLP, VFTLP, probe stations) and how to use it for ESD research purposes.
• June – August 2009 · Visiting scholar at ADI: High Voltage DMOS VFTLP SOA evaluation and DMOS interaction with the ESD protection clamps under VFTLP conditions. TCAD DC and VFTLP calibration and simulation for DMOS devices
• June – November 2008 · Visiting scholar at ADI: Transient VFTLP characterization of relevant ESD and high voltage core device structures. ESD clamp simulation and optimization by TCAD
• January 21^st - February 8^th, 2008 · Visiting scholar at ADI: Gate oxide breakdown under VFTLP stress characterization.
• June – July 2007 · Visiting scholar at ADI: Sentaurus TCAD Suite setup for transient ESD simulations: From Taurus Supreme 4 output to full TLP like simulation
• August 2006 – February 2007 · Research assistant UCF, Device simulation and device simulator calibration. Process simulation of 0.18um STI technology and DC device simulation. Software used by Silvaco: Atlas, Athena.
• April 2005 – July 2006 · Research Assistant USB, Physics based modeling and simulation of emerging devices (SOI and Double gate (DG) MOSFETs). Software: Maple, Sigmaplot, Comsol.
• September – December 2004 · Teaching Assistant USB Solid State Electronics

Publications

1. S. Malobabic, A. Ortiz-Conde, F. J. García Sánchez, "Modeling the Undoped-Body Symmetric Dual-Gate MOSFET", 5th IEEE Int. Caracas Conf. on Cir. Dev. and Sys., (Dominican Republic), pp. 19 -25, Nov. 2004
2. A. Ortiz-Conde, F. J. García Sánchez, S. Malobabic, J. Muci, “Analytic Solution for the drain current of Undoped Symmetric Dual-Gate MOSFETs (Invited)", 2005 Workshop on Compact Modeling (WCM), Anaheim, California, U.S.A, May 2005. See also: http://www.nsti.org/Nanotech2005/WCM2005/
3. A. Ortiz-Conde, F. J. García Sánchez, S. Malobabic “Analytic Solution of the Channel Potential in Undoped Symmetric Dual-Gate MOSFETs", IEEE transactions on Electron Devices, vol. 52, no. 7, pp. 1669 – 1672, July 2005
4. A. Ortiz-Conde, E. Miranda, F. J. García Sanchéz, E. Farkas, and S. Malobabic. “Modeling the Post-Breakdown Current in MOS devices on p-silicon substrate”, IEEE Int. Caribbean Conf. on Cir. Dev. and Sys., 2006
5. A. Ortiz-Conde, F. J. García Sánchez, J. Muci, and S. Malobabic. “A General Analytical solution to the One-Dimensional Undoped Oxide-Silicon-Oxide System”, IEEE Int. Caribbean Conf. on Cir. Dev. and Sys., 2006
6. A. Ortiz-Conde, F. J. García Sánchez, Slavica Malobabic, J. Muci, R Salazar, “Double-Gate MOSFET (invited) ”, 8th International Conference on Solid-State and Integrated-Circuit Technology, October 23-26, 2006, Shanghai, China.
7. F. J. García Sánchez, A. Ortiz-Conde, S. Malobabic, “Applications of Lambert’s Function in Electronics”, Universidad. Ciencia y Tecnología (UCT), no. 41, December 2006.
8. A. Ortiz-Conde, F. J. García-Sánchez, J. Muci, S. Malobabic, J. J. Liou, “A Review of Core Compact Models for Undoped Double-Gate SOI MOSFETs”, IEEE transactions on Electron Devices, vol. 54, no 1, pp. 131-140, January 2007.
9. S. Malobabic, D. F. Ellis, J.A Salcedo, Y. Zhou; J.-J Hajjar, J.J. Liou, “Gate oxide evaluation under very fast transmission line pulse (VFTLP) CDM-type stress”, IEEE Int. Caribbean Conf. on Cir. Dev. and Sys., 2008
10. D. F. Ellis, S. Malobabic, “Prediction of Gate Dielectric Breakdown in the CDM Timescale Utilizing Very Fast Transmission Line Pulsing”, International Reliability Physics Symposium (IRPS) April, 2009
11. S. Malobabic, D. F. Ellis, J.A Salcedo, Y. Zhou; J.-J Hajjar, J.J. Liou, “Very Fast Transient Simulation and Measurement Methodology for ESD Technology Development”, IRPS April, 2009
12. J. J. Liou, S. Malobabic, D. F Ellis, J. A. Salcedo, J.-J Hajjar, Y. Zhou “Transient Safe Operating Area (TSOA) Definition for ESD Applications (invited)”, EOS/ESD Symposium, September 2009.
13. S. Malobabic, J. A. Salcedo, A. W. Righter, J.-J Hajjar, J. J. Liou, “A New ESD Design Methodology for High Voltage DMOS Applications”, EOS/ESD Symposium October 2010.
14. S. Malobabic, J. A. Salcedo, J.-J Hajjar, J. J. Liou, “Analysis of Safe Operating Area of NLDMOS and PLDMOS Transistors Subject to Transient Stresses”, IEEE Transactions on Electron Devices, vol. 57, no. 10, October 2010.

Brief Summary of PhD Thesis Topic and contributions

A methodology to obtain design guidelines for gate oxide input pin protection and high voltage output pin protection in ESD time frame is developed through measurements and Technology Computer Aided Design (TCAD).

A set of parameters from transient measurements to define transient safe operating area (TSOA) is defined. The TSOA parameters are then used to assess effectiveness of protection devices for output and input pins.

The methodology for input pins includes establishing ESD design targets under CDM type stress in low voltage MOS inputs.

The methodology for output pins includes establishing ESD design targets under IEC 61000-4-2/ HMM type stress in high voltage LDMOS outputs. First the assessment of standalone LDMOS robustness in on and off state is performed. Secondly, prediction of DMOS self-protecting conditions is achieved. Prediction of clamp HMM robustness is one based on TLP measurement results. Finally, LDMOS and protection clamp parallel protection conditions are identified.

Honors

• IEEE Electron Devices Society's 2005 Region 9 Outstanding Student Paper
• Honorific mention in undergraduate project and in Master’s thesis
• IEEE Electron Device Society 2008 chapter of the year award
• 2009 IRPS best poster paper award out of 78 papers

IEEE Positions Held

• September 2007 – May 2010 Chapters’ Chair in Orlando section
• Jan 2007 – March 2011 IEEE Electron Device Society (EDS) Chapter Chair in Orlando Section
• Jan – Dec 2007 Components, Packaging, and Manufacturing Technology (CPMT) Chapter Chair in Orlando Section

IEEE Volunteer Work

• Feb 2008 IEEE Orlando Section EDS Mini-Colloquium Comittee Member
• Mar 2010 IEEE Orlando Section EDS Mini-Colloquium Comittee Member
• March 25^th and 26^th, 2010 Organized the EDS Mini Colloquium in Orlando, FL (http://esd.eecs.ucf.edu/index.pl/Seminars and http://eds.ieee.org/images/files/Publications/Newsletters/newsletter_july10.pdf)
• July 2007 – April 2008 Registration Committee Chair for 7th IEEE International Caribbean Conference on Devices, Circuits and Systems, April 28^th to 30^th, 2008, Cancun, Mexico
• February 21^st and 22^nd 2008 Organized the EDS Mini Colloquium in Orlando, FL (http://esd.eecs.ucf.edu/index.pl/Seminars, http://www.ieee.org/portal/cms_docs/society/eds/pubs/newsletters/Newsletter_July08.pdf, and http://www.eecs.ucf.edu/colloq/2007-08/022108.php)
• Sep 2004 Logistics support for 4th Venezuelan Electrical Engineering Congress, Simón Bolívar University, organized by IEEE and Simón Bolívar University, September 7^th to 10^th, 2004
• Jan – Dec 2004 Member of Publications Committee of the 5th IEEE International Caracas Conference on Devices, Circuits and Systems, Punta Cana, Dominican Republic, November 3^rd to 5^th, 2004 (http://pancho.labc.usb.ve/iccdcs2004)
• Feb – May 2002 Member of Publications Committee of the 4th IEEE International Caracas Conference on Devices, Circuits and Systems, Oranjestad, Aruba, Dutch Caribbean, April 17^th to 19^th, 2002